搜索资源列表
8_RISC_CPU
- risc-cpu,简单的cpu设计,强大的功能简洁的设计,精简化-verilog risc_cpu
clk_gen.v
- 时钟发生器,用计数器功能编写的,能更好的潜入模块中,risc-cpu的一部分-clk_gen verilog
RISC_CPU
- 关于risc cpu 的pdf 希望对学习Risc cpu的人有用-Hope that the study of Risc cpu risc cpu pdf
risc_cpu-OK
- 夏宇闻 verilog数字系统设计教程源码 第二版,实现了简单的RISC CPU。印刷版有误,已改正。- A simple RISC CPU Verilog HDL source code. Work well.
BuildingPaPRISCPSystemPinPanPFPGA
- 一个32位 RISC CPU 核心,由Verilog 编写而成-A 32-bit RISC CPU core, written by Verilog
CPU_test
- 设计并通过modelsim仿真软件实现了一个可以在FPGA平台上运行的8位RISC的CPU软核-Design an 8-bit RISC CPU soft core on an FPGA platform and simulate it using ModelSim
实例模块
- 各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench
wb_switch
- wb_switch,opencore,精简指令cpu设计-wb_switch,opencore,risc cpu design。
sw_leds
- 精简指令cpu设计,外扩电路设计,led开发板驱动-wb_sw_leds,opencore,risc cpu design。
display-seg
- 七段数码管驱动电路,fpga,seg7,altera开发板例子-risc-cpu design,seg7,fpga
risc_cpu
- SystemC实现的一个精简指令CPU模型-risc CPU model in systemc
RISC_CPU
- 本例子是一个精简指令集CPU,非常好用经过测试-This example is a RISC CPU, very handy tested
Chapter-13
- 13.2 RISC-CPU设计 13.3 RISC-CPU Testbench设计-13.2 RISC-CPU design 13.3 RISC-CPU Testbench Design
cpu
- RIsc 处理区 内附仿真文件和相关报告-RIsc treatment area containing a simulation files and related reports
all_cpu
- 精简指令集CPU,可完成移位,跳转等简单功能,适用于FPGA学习,本代码使用verilog编写。-RISC CPU, to be completed by the shift, jumps and other simple functions for FPGA learning to write the code using verilog.
TCAM_2
- 经典RISC CPU 设计,和PCI8位指令单片机兼容,值得初学者看一下-Classic RISC CPU design, and PCI8 bit microcontroller compatible instruction, it is worth a look for beginners
CC430_Datasheet
- The Texas Instruments CC430 family of ultralow-power microcontroller system-on-chip (SoC) with integrated RF transceiver cores consists of several devices featuring different sets of peripherals targeted for a wide range of applications. The arch
DLX_verilog
- DLX指令集RISC CPU verilog源码,使用哈佛结构可实现十多种指令-DLX instruction set RISC CPU verilog source code, using the Harvard architecture can achieve more than ten kinds of instruction
CPU
- 运用vhdl硬件描述语言在quartus II开发环境下独立设计与实现了基于精简指令集的五级流水线CPU的设计与实现。该流水CPU包括:取指模块,译码模块,执行模块,访存模块,写回模块,寄存器组模块,控制相关检测模块,Forwarding模块。该CPU在TEC-CA实验平台上运行,并且通过Debugcontroller软件进行单步调试,实验表明,该流水线CPU消除了控制相关、数据相关和结构相关。-Using vhdl hardware descr iption language developm
1121--MSP430FRAM
- 超低功耗微控制器德州仪器MSP430FR698x和MSP430FR598x家庭由多个设备具有不同的套外设。该体系结构,结合7种低功耗模式被优化以实现延长的电池寿命,例如在流量计量应用。该器件具有一个强大的16位RISC CPU,16位寄存器和有助于获得最大编码效率的常数发生器。-Ultra-low-power microcontroller family Texas Instruments MSP430FR698x and MSP430FR598x multiple devices with